Sample Questions

Digital

• Definition of the following :  Clock Skew , Clock Uncertainity , Setup and Hold Time ( Negative and Positive), Ground Bounce , Metastability and its prevention methods , Cause for metastability,Race around condition, Methods to prevent Clock skew ,transitional delays , wire models , Cause for a glitch , Prevention of glitch ,Asynchronous , synchronous and pleisochronous,Multi cycle Path,Recovery Violation ,Ringing,Undershoot and Overshoot .
• State machines  :   Two types of state machines , different encoding styles and their merits and demerits, Precautions to be taken while designing a state machine , Choosing the type of state encoding pertaining to the architecture,Advantages of using state machines ,State reduction technique , fail safe behavior, How state machines are realized in hardware for various encoding styles.
• Designing a Sequence detector , Parity generator other than the tree structure , 16 bit synchronous counter ,Gates implementation using MUX , Latch Using MUX .
• Divide by 3 counter with 50% duty cycle,divide by 2 circuit using single d flip-flop,Multiplier using gates with some assumptions , Direction of rotation detection circuit,Metastability prevention circuit ,Grey counter.
• Synchronizing Asynchronous signals , Data transfer interface between two clock domains .
• Determining the Asynchronous FIFO Depth.
• Ways to increase the Fan out , Calculation of wait states to be added in a particular design ,Calculation of  the max operating frequency for a given digital circuit ,Advantages and disadvantages of Latch and flip flop based design .
• Advantages and Disadvantages of Asynchronous and Synchronous Reset.
• Approach for designing the receive portion of an UART ,Asynchronous FIFO.
• Circuit for a CMOS Tristate Inverter.
• Implementation of a boolean equation using CMOS gates.
• Latch and FLip flop using CMOS gates
• How can a NMI (Non maskable interrupt) be masked in 8085 µP.
• How do we introduce wait states in 8085 µP.

Verilog

• Difference between a net and reg , default values of wire and reg .
• Blocking and non blocking statements  :

                            always @(posedge clk)
                                       b = a;
                            What is the problem with this module and how can it be overcome ?

                        b) always @(b)
                                    a  =  #1 b;
                            always @(b)
                                     #1 a = b;
                            whats the value of a at 5 ns if  b is a sequence  ?

•   Are both the blocks( 1 & 2) the same?

• Advantages  & disadvantages of task and functions .
• Why non blocking are preferred for sequential blocks and blocking for combinational blocks?
• PLI and its use.
• Escaped Identifiers.
• Default width of a parameter.
• Use of $recovery system task
• Advantage of parameters over 'define.
• Named association and its advantages .
• Handling multiple drivers,Unconnected ports
• Access to a register or wire  from some other module.
• Difference between $strobe and $display .
• UDP's.
• Can we log the information using $fdisplay from two always blocks.
• Overriding parameters.
• Forcing of a net inside a block.
• What happens if the timescale defined in different modules are different.
• Handling of bi-directional ports.
• How do u detect Tristate using if and case statements.
• Expanded and collapsed vector.
• Why all inputs used in a block should be in a sensitivity list.

VHDL

• Difference between a signal and a variable .
• Inertial delay , transport delay , delta delay .
• what are Generics ?
• Blocks and guarded blocks.
• what are resolution ,conversion and impure functions.
• Comment on the behavior of variable and signal assignment inside a sequential block.
• what are attributes.
• Use of Packages
• Overloading in VHDL
• Use of generate statement.
• Can a n-dimensional array be declared in VHDL
• Use of configuration.

Synthesis    (Try in VHDL too)

• Mux implementation : using if , case , assign statements and how is it realized ?
• Flip flop implementation with reset , preset and clock enable .
• Proper way for gating clocks.
• Comment on the following 2 blocks output :

                      always @(posedge clk )
                      begin : block2
                                    a = in ;
                                    b = a ;
                      end

• what will be the realized output of the following code

• Try writing code for different state encodings like one hot , binary , grey etc..and realize the output .
• Synthesis flow
• Is disable statement synthesisable ?
• Does it mean that the reg will always result in a flip flop at the output ? If yes give comments ...
• Define :  Critical Path , Slack  , Incremental synthesis , Load violation , Design Rule Check , transitional delay ,Static Timing Analysis , Design Constraints , Behavioral and structural model, Resource  sharing , Partitioning.
• How will a function and task be synthesized which has no timing delays inside it?
• Assuming we don't have the reg facility and only a flip flop module is available , how do we design a register  and what are the various possible methods and which one is the best and why?
• How a latch is inferred and how can it be prevented ?
• Write a code for a bi-directional shift register  , simple arbiter , mod3 counter with 50% duty cycle.
• Some basic scripting commands in DC Shell
• How do we code for a late arriving signal
• Will both of these statements be synthesized same

Simulation

• Interpreted and compiled simulators ,Cycle based Simulators .
• Conservation of simulation Time : how do we achieve it in Verilog and VHDL ?
• Code coverage and how is it done.
• Approaches for designing the stimulus for a given DUT.
• Selection of a Simulator based on the size of  design.
• Board Simulation and how is it done?
• Pre and post synthesis Simulation .
• Formal verification .