Welcome to Simulation
This page has some useful information on simulation using verilog and VHDL.Well
, Simulation plays a vital role in any project ,as the functionality and
features are checked for their conformance to requirements .Here are some
useful information for us.......
Simulation,
Waveform Generation, and Parameters (Tutorial 2)
Simulation
Vector Generation from HDL
SMASH - the screen-shots
gallery
Using Both
VHDL and Verilog for Board-Level Simulation
John
Cooley VHDL vs Verilog
Verification made easy (Coming soon)
Simulator's available in the market 
Model Tech
Verilog XL
VCS , VSS
Verilogger Pro
GMVHDL
FINSIM
Simulators (including
free ones)
