AURELIA JOHANA NURITA

OBJECTIVE:

A Summer 2001 Internship in designing, analyzing, and testing of analog and digital circuits by using CAD tools.

Note: I want to apply for an internship as a guideline to a full time position. I currently use F-1 visa, so I need a sponsorship after graduation.

EDUCATION:

Candidate of M.S., EE, University of Southern California. (Current GPA = 3.3)

Area of interest: VLSI design (expected graduation: December 2001)

B.Sc., EE, Bandung Institute of Technology (ITB) – INDONESIA, Feb 12, 1999.

Related courses:

	MOS VLSI Circuit Design (EE - 477L)
	VLSI System Design (EE - 577b)
	Integrated Circuit (IC) Analysis and Design (EE - 536)
	Logic Design and Switching (EE - 552)

PROJECT DONE:

	5-Stage Pipelined Processor using a RTL style of Verilog.
	Designing a Building Block RISC processor using a RTL style of Verilog.
	31-Stage Ring Oscillator using Magis and HSPICE
	3-Bit D Register using Magis and HSPICE

WORK EXPERIENCE:

Student Worker 1998-1999 PT. TELKOM,

Research and Development (R&D) Division Bandung, INDONESIA.

Re-engineered the Synchronous Digital Hierarchy network in Bogor area, Indonesia.

Student Worker 06/1998 – 08/1998 PT. TELKOM,

Fiber Access Local Network Division Jakarta, INDONESIA.

Assisted the improvement in application of Fiber Access Local Network for Suara

Laboratory assistant 1997-1998 Bandung Institute of Technology

Transmission Lines course. Bandung, INDONESIA.

Four Terminal Circuits course.

COMPUTER SKILLS:

OS WIN98/2000, Unix, Mac, Sun Solaris

VLSI/CAD Tools Verilog, Magic, IRSIM, HSPICE, PSPICE, C++

ACTIVITIES:

Member of EE Students Association (HME) – ITB, Indonesia (1995-1999)

· Boston Academy of English, Olin Center, Kaplan- Boston (1999- August 2000)

· University of Technology in Sydney, Australia (Summer 1995)

REFERENCES: Available upon request.