4.1 Á¶ÇÕ³í¸®¼³°èÀÇ ÀϹÝÀû Á¢±Ù ¹æ¹ý
1) Ç®°íÀÚ ÇÏ´Â ¹®Á¦¸¦ ±â¼úÇÑ´Ù.
2) ÀÔÃâ·Â º¯¼ö¿ÍÀÇ °ü°è¸¦ ¸íÈ®È÷ ÇÏ¿© Áø¸®Ç¥¸¦ ÀÛ¼ºÇÑ´Ù.
3) Ä«³ë(Karnaugh)¸Ê µµÇ¥¹ý¿¡
ÀÇÇØ Ãâ·Â½ÄÀ» °£·«È, ¾ò¾îÁø ½ÄÀ» °öÀÇ ÇÕ(SOP)¶Ç´Â
ÇÕÀÇ °ö(POS)ÀÇ ÇüÅ·ΠǥÇö.
ÃÖ¼ÒÀÇ °ÔÀÌÆ® ÀÔ·Â ¼ö¿Í ÃÖ¼ÒÀÇ °ÔÀÌÆ® ¼ö·Î ±¸¼º.----ÃÖÀûÀÇ ¼³°èÁ¶°Ç
4) ȸ·Î¸¦ ½ÇÇöÇϴµ¥ »ç¿ëµÇ´Â
³í¸®Çü¿¡ ÀûÇÕÇϵµ·Ï °£·«ÈµÈ ½ÄÀ» ¹è¿.
NAND°ÔÀÌÆ®, ¶Ç´Â NOR°ÔÀÌÆ®µé ¸¸À¸·Î, ¶Ç´Â AND-ORÁ¶ÇÕÇÑ °ÔÀÌÆ®µé·Î ¼³°èÇÒ
¼ö
ÀÖµµ·Ï ÇÑ´Ù.
5) ÃÖÁ¾ÀÇ ³í¸®È¸·Îµµ¸¦ ±×¸°´Ù.
6) °¢°¢ÀÇ º¯¼öµé°ú À̵éÀÇ
ÀÛµ¿·¹º§À» Ç¥½ÃÇÏ°í, °¡´ÉÇÑ ÇÑ Áø¸®Ç¥¸¦ Æ÷ÇÔÇÏ¿© ¼³°è°úÁ¤À»
¹®¼È ÇÑ´Ù.
[¿¹Á¦ 4.1] 2Áø 2ºñÆ®ÀÎ 2 x 2 ½Â»ê±âÀÇ Á¶ÇÕȸ·Î¸¦ ¼³°èÇ϶ó.
- 4°³ÀÇ ÀԷº¯¼ö (A1, A0, B1, B0)¿Í 4°³ÀÇ Ãâ·Â º¯¼ö (P3, P2, P1, P0)°¡ ÇÊ¿ä.
- 2X2ºñÆ® °ö¼À¿¡ ÀÖ¾îÀÇ ÃÖ´ë°ª(310 x 310 = 910)ÀÌ 4ºñÆ®À̹ǷΠ4°³ÀÇ Ãâ·Âº¯¼ö°¡ ÇÊ¿äÇÏ´Ù.
[Ãâ·ÂSOP½Ä]
P3
= f(A1, A0, B1,
B0) = ¢²(15)
P2 = f(A1, A0,
B1, B0) = ¢²(10, 11, 14)
P1 = f(A1, A0,
B1, B0) = ¢²(6, 7, 9, 11, 13,
14)
P0 = f(A1, A0,
B1, B0) = ¢²(5, 7, 13, 15)
[°£·«È µÈ °¢ Ãâ·Â½Ä]
P3
= A1A0B1B0,
P2 = A1A0'B1
+ A1B1B0'
P1 = A1'A0B1
+ A0B1B0'
+ A1B1'B0
+ A1A0'B0
P0 = A0B0
-----------------------------------
ÀÔ·Â
Ãâ·Â
-----------------------------------
A1 A0
B1 B0
P0 P1
P2 P3
-----------------------------------
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 0 1 0
0 0 0 0
0 0 1 1
0 0 0 0
0 1 0 0
0 0 0 0
0 1 0 1
0 0 0 1
0 1 1 0
0 0 1 0
0 1 1 1
0 0 1 1
1 0 0 0
0 0 0 0
1 0 0 1
0 0 1 0
1 0 1 0
0 1 0 0
1 0 1 1
0 1 1 0
1 1 0 0
0 0 0 0
1 1 0 1
0 0 1 1
1 1 1 0
0 1 1 0
1 1 1 1
1 0 0 1
-----------------------------------
4.2 µðÁöÅÐ ÁýÀûȸ·ÎÀÇ °³¿ä
- SSI(¼Ò±Ô¸ð ÁýÀûȸ·Î) : 2ÀÔ·Â µî°¡ °ÔÀÌÆ®°¡ ´ë°³ 10°³¹Ì¸¸
- MSI(Áß±Ô¸ð ÁýÀûȸ·Î) : 100°³Á¤µµÀÇ °ÔÀÌÆ®
- LSI(´ë±Ô¸ð ÁýÀûȸ·Î) : ¾à 102¡104°³ Á¤µµÀÇ °ÔÀÌÆ®
- VLSI(ÃʱԸð ÁýÀûȸ) : 104¡106°³Á¤µµÀÇ °ÔÀÌÆ®
- °¢Á¾ µðÁöÅÐ IC ³í¸®±º(logic family) :
TTL(Transistor-Transistor logic), ECL(Emitter-Coupled Logic)
CMOS(Complemenetary Metal-Oxide Semiconductor logic)µî
ºÎ ³í¸®±º(subfamily), ÀúÀü·Â(low power), °í¼Ó(Highspeed: H),
Àú Àü·Â ¼ÒƮŰ(Schottky: S), °í±Þ ÀúÀü·Â ¼îƮŰ(advanced low
power schottky: ALS)µî
- ³í¸®ÀÇ Ç¥Çö¹æ½Ä : Áø¸®Ç¥, Logic Diagram, Boolean Equ.
4.3 µðÄÚ´õ
µðÄÚ´õ(decoder) : ÇϳªÀÇ ÄÚµå·Î ³ªÅ¸³»´Â ÀÔ·Â º¯¼öµéÀÇ
¼Â(set)À» ¶Ç ´Ù¸¥ ÄÚµå·Î Ãâ·Â
º¯¼öµéÀÇ ¼ÂÀ¸·Î º¯È¯ÇÏ´Â Á¶ÇÕ ³í¸® ȸ·Î.
- n°³ÀÇ ÀԷ¿¡ ´ëÇÏ¿© µðÄÚ´õ´Â ÃÖ´ë 2©ú°³ÀÇ Ãâ·Â.
- 2©ú°³ÀÇ Ãâ·Â °ªÀº 0¿¡¼ 2©ú -1±îÁöÀÇ ¹üÀ§.
- ¾î¶² µðÄÚ´õ´Â 2©ú°³ º¸´Ù ÀûÀº Ãâ·ÂÀÇ °³¼öµµ ÀÖ´Ù.
-
¿¹ : 3 to 8 µðÄÚ´õ
4.4 ÀÎÄÚ´õ
ÀÎÄÚ´õ(encoders) : ÀÎÄÚ´õ´Â µðÄÚ´õ¿Í ¿ª±â´É
- 2©ú °³ÀÇ ÀԷµé·ÎºÎÅÍ n°³ÀÇ Ãâ·Â.
- ¿¹ : 8 to 3 ÀÎÄÚ´õ
Decode
<----------
[ n- bit 2Áø¼ö ]
[ 2©ú °³ÀÇ ¶óÀÎ ]
---------->
Encode
4.5 ¸ÖƼÇ÷º¼/µð¸ÖƼÇ÷º¼
¸ÖƼÇ÷º¼´Â n°³ÀÇ ÀԷ¿¡ ´ëÇØ ÇÑ °³¸¦ ¼±ÅÃÇØ Ãâ·Â
-
4-to-1 ¸ÖƼÇ÷º¼´Â 2°³ÀÇ ¼±ÅÃÁ¦¾î ÀÔ·Â, 8-to-1 ¸ÖƼÇ÷º¼´Â 3°³ÀÇ
¼±Åà ÀÔ·Â
-
µð¸ÖƼÇ÷º¼´Â ¸ÖƼÇ÷º¼ÀÇ ¹Ý´ë±â´É
4.6 °¡»ê±â¿Í °¨»ê±â
¹Ý°¡»ê±â(half-adder)
S = f(X,
Y) = ¢²(1, 2) = X'Y + XY'
C-out
= f(X, Y) = ¢²(3) = XY
Àü°¡»ê±â(full-adder)ÀÇ ÇÕ°ú ij¸®¿¡ ´ëÇÑ ºÎ¿ï½Ä
S
= f(X, Y, C-in) = ¢²(1, 2, 4, 7)
C-out = f(X, Y, C-in) = ¢²(3, 5, 6, 7)
S
= X'Y' (C-in) + X'Y (C-in)' + XY' (C-in)' + XY (C-in)
C-out = XY + X (C-in) + Y (C-in)
¹Ý °¨»ê±â¿¡ ´ëÇÑ Ãâ·Â½Ä
D
= f(X, Y) = ¢²(1, 2) = X'Y + XY'
B-out = f(X, Y) = ¢²(1) = X'Y
Àü °¨»ê±â
D
= f(X, Y, B-in) = ¢²(1, 2, 4, 7)
B-out = f(X, Y, B-in) = ¢²(1, 2, 3, 7) = X'Y + X'(B-in) + Y(B-in)