-- mux4to1_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mux4to1_1bit IS
               PORT (  a, b, c, d : in std_logic;
                                     s   : in std_logic_vector(1 downto 0);
                                     o   : out std_logic);
            END mux4to1_1bit;

            ARCHITECTURE maxpld OF mux4to1_1bit IS
            BEGIN
               with s select 
                  o <=  a when "00",
                           b when "01",
                           c when "10",
                           d when others;
            END maxpld;
 

   [VHDL 2]
            -- mux4to1_1bit_2.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mux4to1_1bit_2 IS
            PORT (  a, b, c, d : in std_logic;
                                  s   : in std_logic_vector(1 downto 0);
                                  o   : out std_logic);
            END mux4to1_1bit_2;

            ARCHITECTURE maxpld OF mux4to1_1bit_2 IS
            BEGIN
               process(s, a, b, c, d)
                  begin
                     case s is
                        when "00" => o <=a;
                        when "01" => o <=b;
                        when "10" => o <=c;
                        when others => o <=d;
                  end case;
               end process; 
             END maxpld;