-- upcounter_3bit.vhd

            LIBRARY ieee; 
            USE ieee.std_logic_1164.all; 
            USE ieee.std_logic_signed.all;
            USE ieee.std_logic_arith.all; 

            ENTITY upcounter_3bit IS 
            PORT (  clk, reset  : in std_logic; 
                       count_out  : out std_logic_vector(2 downto 0));
            END upcounter_3bit; 

            ARCHITECTURE maxpld OF upcounter_3bit IS 
            signal tmp : std_logic_vector(2 downto 0);
            BEGIN  
               count_out <= tmp;
               process(clk, reset)
               begin
                  if (reset= '1') then
                     tmp <= "000";
                  elsif (clk='1' and clk'event) then
                     tmp <= tmp + '1';
                  end if;
               end process;
             END maxpld;