-- updncounter_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;
            USE ieee.std_logic_arith.all;

            ENTITY updncounter_4bit IS
            PORT (clk, reset, enable, load, up_down : in std_logic;
                                                     databus       : in std_logic_vector(3 downto 0);
                                                   count_out      : out std_logic_vector(3 downto 0));           
            END updncounter_4bit;

            ARCHITECTURE maxpld OF updncounter_4bit IS 
            signal tmp : std_logic_vector(3 downto 0);
            signal clkenable : std_logic;
            constant zero : std_logic_vector := "0000";

            BEGIN
               count_out <= tmp;
               clkenable <= clk and enable;
               process(clkenable, reset, load)
                  begin
                     if (reset='1') then
                        tmp <= zero;
                     elsif (clkenable='1' and clkenable'event) then
                        if(load='1') then
                           tmp <= databus;
                        elsif (up_down='1') then
                           tmp <= tmp + '1';
                        else
                           tmp <= tmp - '1';
                        end if;
                     end if;
               end process;
              END maxpld;