-- and_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY and_1bit IS
            PORT (  x, y   : in std_logic;
                           o    : out std_logic);
            END and_1bit;

            ARCHITECTURE maxpld OF and_1bit IS 
            BEGIN

            o <= x AND y;

            END maxpld;