-- or_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY or_1bit IS
            PORT (  x, y   : in std_logic;
                            o   : out std_logic);
            END or_1bit;

           ARCHITECTURE maxpld OF or_1bit IS 
           BEGIN

           o <= x OR y;

           END maxpld;