-- mux2to1_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mux2to1_4bit IS
               PORT (  a, b : in std_logic_vector( 3 downto 0);
                               s : in std_logic;
                               o : out std_logic_vector( 3 downto 0));
            END mux2to1_4bit;

            ARCHITECTURE maxpld OF mux2to1_4bit IS
            BEGIN 
                  PROCESS(a,b,s)
                     BEGIN
                        IF(s='0') THEN
                           o <= a;
                        ELSE
                           o <= b;
                        END IF;
                  END PROCESS;

            END maxpld;