-- mux4to1_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mux4to1_4bit IS
            PORT (  a, b, c, d : in std_logic_vector(3 downto 0);
                                  s   : in std_logic_vector(1 downto 0);
                                  o   : out std_logic_vector(3 downto 0));
            END mux4to1_4bit;

            ARCHITECTURE maxpld OF mux4to1_4bit IS
            BEGIN
               process(s, a, b, c, d)
                  begin
                     case s is
                                when "00" => o <=a;
                                when "01" => o <=b;
                                when "10" => o <=c;
                                when others => o <=d;
                     end case;
               end process; 
             END maxpld;