-- mux6to1_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mux6to1_4bit IS
            PORT ( a, b, c, d, e, f : in std_logic_vector(3 downto 0);
                                       s    : in std_logic_vector(2 downto 0);
                                       o    : out std_logic_vector(3 downto 0));
            END mux6to1_4bit;

            ARCHITECTURE maxpld OF mux6to1_4bit IS
            BEGIN
               process(s, a, b, c, d, e, f)
                  begin
                     case s is
                                 when "000" => o <=a;
                                 when "001" => o <=b;
                                 when "010" => o <=c;
                                 when "011" => o <=d;
                                 when "100" => o <=e;
                                 when "101" => o <=f;
                                 when others => o <= "----";
                      end case;
                   end process;  
            END maxpld;