-- mux4to1_4bit_en.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mux4to1_4bit_en IS
            PORT ( a, b, c, d : in std_logic_vector(3 downto 0);
                          enable  : in std_logic;
                                 s   : in std_logic_vector(1 downto 0);
                                 o   : out std_logic_vector(3 downto 0));
            END mux4to1_4bit_en;

            ARCHITECTURE maxpld OF mux4to1_4bit_en IS
            BEGIN
               process(s)
                  begin
                     if (enable = '0') then
                        case s is
                                     when "00" => o <=a;
                                     when "01" => o <=b;
                                     when "10" => o <=c;
                                     when others => o <=d;
                        end case;
                     else 
                        o <= "0000";
                     end if;
                  end process;  
             END maxpld;