[VHDL]
--
dec2to4.vhd
LIBRARY
ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY
dec2to4 IS
PORT ( a : in std_logic_vector(1 downto 0);
o : out std_logic_vector(3 downto 0));
END dec2to4 ;
ARCHITECTURE
maxpld OF dec2to4 IS
BEGIN
PROCESS
begin
case a is
when "00" => o <= "0001";
when "01" => o <= "0010";
when "10" => o <= "0100";
when others => o <= "1000";
end case;
END PROCESS;
END maxpld;
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