-- adder_8bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY adder_8bit IS
            PORT (  a, b   : in unsigned(7 downto 0);
                            c    : out integer);
            END adder_8bit;

            ARCHITECTURE maxpld OF adder_8bit IS 
            BEGIN
               c <= conv_integer(a + b); 
            END maxpld;