-- parity_8bit_var.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY parity_8bit_var IS
            PORT (  word  : in bit_vector(7 downto 0);
                        parity  : out bit);
            END parity_8bit_var;

            ARCHITECTURE maxpld OF parity_8bit_var IS 
            BEGIN
               process
               variable result : bit;
               begin
                  result := '0';
                  for i in 0 to 7 loop
                  result := result xor word(i);
                  end loop;
  
                  parity <= result;

               end process;
             END maxpld;