-- and_1bit_3.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY and_1bit_3 IS
            PORT (  x, y, z   : in std_logic;
                              o     : out std_logic);
            END and_1bit_3;

            ARCHITECTURE maxpld OF and_1bit_3 IS 
            BEGIN

               o <= x AND y AND z;

            END maxpld;
 

   [VHDL2]

            -- and_1bit_3_1.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY and_1bit_3_1 IS
            PORT (  x, y, z   : in bit;
                              o     : out bit);
            END and_1bit_3_1;

            ARCHITECTURE maxpld OF and_1bit_3_1 IS 
            BEGIN

               o <= x AND y AND z;

            END maxpld;
 

   [VHDL3]
  
            -- and_1bit_3_var.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY and_1bit_3_var IS
            PORT (  x, y, z   : in bit;
                              o     : out bit);
            END and_1bit_3_var;

            ARCHITECTURE maxpld OF and_1bit_3_var IS 
            BEGIN
               process
               variable tem : bit;
               begin 
                  tem := '1';
                  tem := x and tem;
                  tem := y and tem;
                  tem := z and tem;
                    o <= tem;
               end process;
            END maxpld;