-- dncounter_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;
            USE ieee.std_logic_arith.all;

            ENTITY dncounter_4bit IS
            PORT (clk, reset, enable, load : in std_logic;
                                        databus     : in std_logic_vector(3 downto 0);
                                      count_out    : out std_logic_vector(3 downto 0));           
            END dncounter_4bit;

            ARCHITECTURE maxpld OF dncounter_4bit IS 
            signal tmp : std_logic_vector(3 downto 0);
            signal clkenable : std_logic;
            constant zero : std_logic_vector := "0000";

            BEGIN
               count_out <= tmp;
               clkenable <= clk and enable;
               process(clkenable, reset, load)
                  begin
                  if (reset='1') then
                     tmp <= zero;
                  elsif (clkenable='1' and clkenable'event) then
                     if(load='1') then
                        tmp <= databus;
                     else
                        tmp <= tmp - '1';
                     end if;
                  end if;
               end process;
              END maxpld;