-- upcounter_time.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;
            USE ieee.std_logic_arith.all;

            ENTITY upcounter_time IS
               PORT (clk, reset, enable, load : in std_logic;
                                           databus     : in std_logic_vector(5 downto 0);
                                         count_out    : out std_logic_vector(5 downto 0));           
            END upcounter_time;

            ARCHITECTURE maxpld OF upcounter_time IS 
            signal tmp : std_logic_vector(5 downto 0);
            signal clkenable : std_logic;
            constant lastvalue : std_logic_vector :="111011";
            constant initialvalue : std_logic_vector :="000000";
            BEGIN
               count_out <= tmp;
               clkenable <= clk and enable;
               process(clkenable, reset, load)
               begin
                  if (reset='1') then
                      tmp <= initialvalue;
                  elsif (clkenable='1' and clkenable'event) then
                     if(load='1') then
                        tmp <= databus;
                     elsif (tmp = lastvalue) then
                        tmp <= initialvalue;
                     else
                        tmp <= tmp + '1';
                     end if;
                  end if;
               end process;
             END maxpld;