-- johncnt_5bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY johncnt_5bit IS
            PORT (clk, reset : in std_logic;
                     count_out : out std_logic_vector(4 downto 0));           
            END johncnt_5bit;

            ARCHITECTURE maxpld OF johncnt_5bit IS 
            signal tmp : std_logic_vector(4 downto 0);

            BEGIN
               count_out <= tmp;
               process (clk, reset)
               begin
                  if (reset='1') then
                     tmp <= "00000";
                 elsif (clk='0' and clk'event) then
                     tmp <= tmp(3 downto 0) & not(tmp(4));
                 end if;
              end process;
            END maxpld;