-- graycnt_3bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            entity graycnt_3bit is
            port ( clk, reset  : in std_logic;
                   count_out   : out std_logic_vector(2 downto 0)); 
            end graycnt_3bit;

            architecture maxpld of graycnt_3bit is
            signal tmp : std_logic_vector(2 downto 0);
            constant zero : std_logic_vector := "000";
            begin 
            count_out <= tmp;
               process(clk, reset)
               begin
                  if (reset='1') then
                     tmp <= zero;
                  elsif (clk='0' and clk'event) then
                     case tmp is
                              when "000" => tmp <= "001";
                              when "001" => tmp <= "011";
                              when "010" => tmp <= "110";
                              when "011" => tmp <= "010";
                              when "100" => tmp <= "000";
                              when "101" => tmp <= "100";
                              when "110" => tmp <= "111";
                              when "111" => tmp <= "101";
                              when others => tmp <= "000";
                     end case;   
                  end if;
               end process;
             end maxpld;