--pipeadder.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;

            ENTITY pipeadder IS
            port ( clk    : in std_logic;
                   inbus  : in std_logic_vector(7 downto 0);
                  outbus : out std_logic_vector(8 downto 0));
            END pipeadder;

            ARCHITECTURE maxpld OF pipeadder IS
                signal reg_a : std_logic_vector(7 downto 0);
                signal reg_b : std_logic_vector(8 downto 0);
            BEGIN
                outbus <= reg_b;
                process(clk)
                begin
                    if (clk='1' and clk'event) then
                        reg_a <= inbus;
                        reg_b <= ('0' & reg_a) + ('0' & inbus);
                   end if;
                end process; 
             END maxpld;