-- fulladder_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY fulladder_1bit IS
            PORT (  a, b, c_in  : in std_logic;
                           s, c_out : out std_logic);
            END fulladder_1bit;

            ARCHITECTURE maxpld OF fulladder_1bit IS 
            BEGIN
                s <= ((a xor b) xor c_in);
                c_out <= (a and b) or (a and c_in) or (b and c_in);
            END maxpld;