-- pipe_adder_sub.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;
 

            ENTITY pipe_adder_sub IS
            PORT ( clk, sel : in std_logic;
                         inbus  : in std_logic_vector(7 downto 0);
                        outbus : out std_logic_vector(8 downto 0));
            END pipe_adder_sub;

            ARCHITECTURE maxpld OF pipe_adder_sub IS
            signal reg_a : std_logic_vector(7 downto 0);
            signal reg_b : std_logic_vector(8 downto 0);
            BEGIN
                outbus <= reg_b;
                process(clk)
                begin
                    if (clk='1' and clk'event) then
                        if (sel='1') then
                            reg_a <= inbus;
                            reg_b <= ('0' & reg_a) + ('0' & inbus);
                       else
                            reg_a <= inbus;
                            reg_b <= ('0' & reg_a) - ('0' & inbus);
                       end if;
                    end if;
                end process;       
            END maxpld;