-- Binary Coded Decimal_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;

            ENTITY bcd_4bit IS
                port ( s     : in std_logic_vector(3 downto 0);
                        c_in  : in std_logic;
                       s_out : out std_logic_vector(3 downto 0);
                       c_out : out std_logic);
            END bcd_4bit;

            ARCHITECTURE maxpld OF bcd_4bit IS
            BEGIN
                process(s, c_in)
                begin
                    if (c_in='0') then
                        if (s="1010") then
                            s_out <= "0000";
                            c_out <= '1';
                        elsif (s="1011") then
                            s_out <= "0001";
                            c_out <= '1';
                        elsif (s="1100") then
                            s_out <= "0010";
                            c_out <= '1';
                        elsif (s="1101") then
                            s_out <= "0011";
                            c_out <= '1';
                        elsif (s="1110") then
                            s_out <= "0100";
                            c_out <= '1';
                        elsif (s="1111") then
                            s_out <= "0101";
                            c_out <= '1';
                        else 
                            s_out <= s;
                            c_out <= '0';
                        end if;
                    end if;
               end process;       
             END maxpld;