[VHDL]
--
Moore Machine.vhd
LIBRARY
ieee;
USE ieee.std_logic_1164.all;
ENTITY
moore IS
PORT ( reset, clk : in std_logic;
ph1, ph2, ph3 : out std_logic);
END moore;
ARCHITECTURE
maxpld OF moore IS
constant s0 : std_logic_vector(2 downto 0) := "110";
constant s1 : std_logic_vector(2 downto 0) := "010";
constant s2 : std_logic_vector(2 downto 0) := "111";
constant s3 : std_logic_vector(2 downto 0) := "011";
constant s4 : std_logic_vector(2 downto 0) := "101";
constant s5 : std_logic_vector(2 downto 0) := "001";
signal c_state, n_state : std_logic_vector(2 downto 0);
signal tmp_ph3 : std_logic;
signal ph : std_logic_vector(2 downto 0);
BEGIN
p1 : process(clk, reset)
begin
if (reset='1') then
c_state <= s0;
elsif (clk='1' and clk'event) then
c_state <= n_state;
end if;
end process;
p2
: process(c_state)
begin
case c_state is
when s0 => ph <= s0;
n_state <= s1;
when s1 => ph <= s1;
n_state <= s2;
when s2 => ph <= s2;
n_state <= s3;
when s3 => ph <= s3;
n_state <= s4;
when s4 => ph <= s4;
n_state <= s5;
when others => ph <= s5;
n_state <= s0;
end case;
ph1 <= ph(2);
ph2 <= ph(1);
tmp_ph3 <= ph(0);
end process;
p3
: process(clk)
begin
if (clk='0' and clk'event) then
ph3 <= tmp_ph3;
end if;
end process;
END maxpld;
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