-- Mealy Machine 3.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;

            ENTITY fsm3 IS
            PORT ( reset, x, clk : in std_logic;
                                  z    : out std_logic);
            END fsm3;

            ARCHITECTURE maxpld OF fsm3 IS
            type state is (s0, s1, s2);
            signal c_state, n_state : state;
            BEGIN
            Sync : process(clk, reset)
                begin
                    if (reset='0') then
                        c_state <= s0;
                    elsif (clk='1' and clk'event) then
                        c_state <= n_state;
                    end if; 
                end process; 

            comb : process(c_state, x)
            begin
                case c_state is
                    when s0 => z <= '0';
                        if (x='0') then
                            n_state <= s0;
                        else
                            n_state <= s1;
                        end if;
                    when s1 => z <= '0';
                        if (x='0') then
                            n_state <= s0;
                        else
                            n_state <= s2;
                        end if;
                    when s2 =>
                        if (x='0') then
                            z <= '1';
                            n_state <= s0;
                        else
                            z <= '1';
                            n_state <= s1;
                        end if;
                 end case;
              end process;
            END maxpld;