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   1BIT NAND GATE : nand_1bit.gdf
                              nand_1bit.vhd

   [SCH]

 

   [VHDL]

            -- nand_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY nand_1bit IS
            PORT (  x, y   : in std_logic;
                            o   : out std_logic);
            END nand_1bit;

            ARCHITECTURE maxpld OF nand_1bit IS 
            BEGIN

            o <= x NAND y;

            END maxpld;

 


   [RESULT]

 
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