-- nor_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY nor_1bit IS
            PORT (  x, y   : in std_logic;
                            o   : out std_logic);
            END nor_1bit;

            ARCHITECTURE maxpld OF nor_1bit IS 
            BEGIN

            o <= x NOR y;

            END maxpld;