-- halfadd_1bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY halfadd_1bit_1bit IS
            PORT (  x, y   : in std_logic;
                         s, c  : out std_logic);
            END halfadd_1bit;

            ARCHITECTURE maxpld OF halfadd_1bit IS 
            BEGIN

            s <= x XOR y;
            c <= x AND y;

            END maxpld;