[VHDL]
--
dec3to8.vhd
LIBRARY
ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY
dec3to8 IS
PORT ( a : in std_logic_vector(2 downto 0);
o : out std_logic_vector(7 downto 0));
END dec3to8 ;
ARCHITECTURE
maxpld OF dec3to8 IS
BEGIN
PROCESS
begin
case a is
when "000" => o <= "00000001";
when "001" => o <= "00000010";
when "010" => o <= "00000100";
when "011" => o <= "00001000";
when "100" => o <= "00010000";
when "101" => o <= "00100000";
when "110" => o <= "01000000";
when others => o <= "10000000";
end case;
END PROCESS;
END maxpld;
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