-- dff_re.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY dff_re IS
            PORT (  data, clk   : in std_logic;
                                 q     : out std_logic);
            END dff_re;

            ARCHITECTURE maxpld OF dff_re IS 
            BEGIN
               process(clk)
               begin
                 if (clk='1' and clk'event) then
                    q <= data;
                 end if;
               end process;
             END maxpld;