-- dff_fe.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY dff_fe IS
            PORT (  data, clk   : in std_logic;
                                 q     : out std_logic);
            END dff_fe;

            ARCHITECTURE maxpld OF dff_fe IS 
            BEGIN
               process(clk)
               begin
                  if (clk='0' and clk'event) then
                     q <= data;
                  end if;
               end process;
            END maxpld;