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   DLATCH_Enable 0 : dlatch_en2.gdf
                              dlatch_en2.vhd

   [SCH]

   [VHDL]

            -- dlatch_en2.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY dlatch_en2 IS
            PORT (  data, enable   : in std_logic;
                                        q    : out std_logic);
            END dlatch_en2;

            ARCHITECTURE maxpld OF dlatch_en2 IS 
            BEGIN
               process(data, enable)
               begin
                  if (enable='0') then
                     q <= data;
                  end if;
               end process;
             END maxpld;
 


   [RESULT]
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