-- dff_re_asP.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY dff_re_asP IS
            PORT (  data, clk, preset   : in std_logic;
                                           q       : out std_logic);
            END dff_re_asP;

            ARCHITECTURE maxpld OF dff_re_asP IS 
            BEGIN
               process(clk, preset)
                  begin
                     if (preset = '0') then
                        q <= '1';
                     elsif(clk='1' and clk'event) then
                     q <= data;
                     end if;
               end process;
             END maxpld;