-- dff_re_asRP.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY dff_re_asRP IS
            PORT (  data, clk, reset, preset  : in std_logic;
                                                 q         : out std_logic);
            END dff_re_asRP;

            ARCHITECTURE maxpld OF dff_re_asRP IS 
            BEGIN
               process(clk, reset, preset)
                  begin
                     if (reset = '0') then
                        q <= '0';
                     elsif (preset='0') then
                        q <= '1';
                  elsif(clk='1' and clk'event) then
                        q <= data;
                  end if;
               end process;
            END maxpld;