-- dff_re_sR.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY dff_re_sR IS
            PORT (  data, clk, reset   : in std_logic;
                                         q       : out std_logic);
            END dff_re_sR;

            ARCHITECTURE maxpld OF dff_re_sR IS 
            BEGIN
               process(clk, reset)
               begin
                  if (clk='1' and clk'event) then
                     if (reset = '0') then
                         q <= '0';
                     else
                         q <= data;
                     end if;
                  end if;
               end process;
             END maxpld;