-- adder_int_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY adder_int_4bit IS
            PORT (  a, b   : in integer range 0 to 15;
                           c    : out integer range 0 to 15);
            END adder_int_4bit;

            ARCHITECTURE maxpld OF adder_int_4bit IS 
            BEGIN
               c <= a + b; 
            END maxpld;