-- mul_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY mul_4bit IS
            PORT (  a, b   : in unsigned(3 downto 0);
                           c    : out integer);
            END mul_4bit;

            ARCHITECTURE maxpld OF mul_4bit IS 
            BEGIN
               c <= conv_integer(a * b); 
            END maxpld;