-- adder_4bit_4.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY adder_4bit_4 IS
            PORT (  a, b, c, d  : in unsigned(3 downto 0);
                                z      : out integer);
            END adder_4bit_4;

            ARCHITECTURE maxpld OF adder_4bit_4 IS 
            BEGIN
               z <= conv_integer(a + b + c + d);
            END maxpld;