-- adder_4bit_4_2.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            ENTITY adder_4bit_4_2 IS
            PORT (  a, b, c, d  : in unsigned(3 downto 0);
                                z      : out integer);
            END adder_4bit_4_2;

            ARCHITECTURE maxpld OF adder_4bit_4_2 IS 
               signal e : integer;
               signal f  : integer;

            BEGIN
               e <= conv_integer(a + b);
                f <= conv_integer(c + d);
               z <= conv_integer(e + f);
            END maxpld;