-- ringcnt_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;

            entity ringcnt_4bit is
               port ( clk, reset  : in std_logic;
               count_out   : out std_logic_vector(3 downto 0));
            end ringcnt_4bit;

            architecture maxpld of ringcnt_4bit is
               signal tmp : std_logic_vector(3 downto 0);
            begin 
               count_out <= tmp;
               process(clk, reset)
               begin
                  if (reset='0') then
                     tmp <= "0001";
                  elsif (clk='0' and clk'event) then
                     tmp <= tmp(2 downto 0) & tmp(3);
                  end if;
               end process;
             end maxpld;