[VHDL]
--
count999.vhd
LIBRARY
ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
ENTITY
count999 IS
PORT( clk, reset : in std_logic;
out_3 : out std_logic_vector(3 downto 0);
out_2 : out std_logic_vector(3 downto 0);
out_1 : out std_logic_vector(3 downto 0));
END count999;
ARCHITECTURE
maxpld OF count999 IS
signal tmp_d100 : std_logic_vector(3 downto 0);
signal tmp_d10 : std_logic_vector(3 downto 0);
signal tmp_d1 : std_logic_vector(3 downto 0);
constant zero : std_logic_vector := "0000";
constant nine : std_logic_vector := "1001";
BEGIN
out_3 <= tmp_d100;
out_2 <= tmp_d10;
out_1 <= tmp_d1;
process(clk, reset)
begin
if (reset='1') then
tmp_d100 <= zero;
tmp_d10 <= zero;
tmp_d1 <= zero;
elsif (clk='1' and clk'event) then
if (tmp_d1=nine) then
tmp_d1 <= zero;
if (tmp_d10=nine) then
tmp_d10 <= zero;
if (tmp_d100=nine) then
tmp_d100 <= zero;
else
tmp_d100 <= tmp_d100 + '1';
end if;
else
tmp_d10 <= tmp_d10 + '1';
tmp_d100 <= tmp_d100;
end if;
else
tmp_d1 <= tmp_d1 + '1';
tmp_d10 <= tmp_d10;
tmp_d100 <= tmp_d100;
end if;
end if;
end process;
END maxpld;
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