-- fulladder_1.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;
            USE ieee.std_logic_signed.all;

            ENTITY fulladder_1 IS
            PORT( a, b, cin  : in std_logic;
                    sum, cout  : out std_logic);
            END fulladder_1;

            ARCHITECTURE maxpld OF fulladder_1 IS
                signal s0, s1, s2 : std_logic;
            BEGIN 
                s0  <= a xor b;
                s1  <= a and b;
                sum <= s0 xor cin;
                s2 <= s0 and cin;
                cout <= s1 or s2;
            END maxpld;