-- fulladder_2.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;
            USE ieee.std_logic_signed.all;

            ENTITY fulladder_2 IS
            PORT( a, b, cin  : in std_logic;
                    sum, cout  : out std_logic);
            END fulladder_2;

            ARCHITECTURE maxpld OF fulladder_2 IS
            BEGIN
               process(a,b,cin)
               variable tmp : std_logic_vector(2 downto 0);
               begin
                  tmp := a & b & cin;
                  case tmp is
                       when "000" => sum <= '0';
                                cout <= '0';
                       when "001" | "010" | "100" => sum <= '1';
                                 cout <= '0';
                       when "011" | "101" | "110" => sum <= '0';
                                 cout <= '1';
                       when "111" => sum <= '1';
                                 cout <= '1';
                       when others => sum <= '0';
                                 cout <= '0';            
                  end case;
                end process;   
            END maxpld;