-- fulladder_4bit.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_arith.all;
            USE ieee.std_logic_signed.all;

            ENTITY fulladder_4bit IS
            PORT( cin  : in std_logic;
                     a, b  : in std_logic_vector(3 downto 0);
                     sum  : out std_logic_vector(3 downto 0);
                     cout  : out std_logic);
            END fulladder_4bit;

            ARCHITECTURE maxpld OF fulladder_4bit IS
            begin
               process(cin, a, b)
               variable carry : std_logic;
               begin
                    carry := cin;
                    for i in 0 to 3 loop
                        sum(i) <= a(i) xor b(i) xor carry;
                        carry  := (carry and (a(i) xor b(i))) or (a(i) and b(i));
                    end loop;
                    cout <= carry;
               end process;   
             END maxpld;