-- multi_4by4.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
            USE ieee.std_logic_signed.all;

            ENTITY multi_4by4 IS
                port ( a, b : in std_logic_vector(3 downto 0);
                          prd : out std_logic_vector(7 downto 0));
            END multi_4by4;

            ARCHITECTURE maxpld OF multi_4by4 IS
            signal p0,p1,p2,p3 : std_logic_vector(7 downto 0);
            constant zero : std_logic_vector := "00000000";
            BEGIN
                process(a, b)
                begin
                    if (b(0)='1') then 
                        p0 <= ("0000" & a);
                    else 
                        p0 <= zero;
                    end if;
                    if (b(1)='1') then 
                        p1 <= ("000" & a & '0');
                    else 
                        p1 <= zero;
                    end if;
                    if (b(2)='1') then 
                        p2 <= ("00" & a & "00");
                    else 
                        p2 <= zero;
                    end if;
                    if (b(3)='1') then 
                        p3 <= ('0' & a & "000");
                    else 
                        p3 <= zero;
                    end if;
                        prd <= (p3 + p2) + (p1 + p0);
               end process;       
             END maxpld;