-- t_ff.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;

            ENTITY t_ff IS
            port ( t, clk : in std_logic;
                          q : buffer std_logic);
            END t_ff;

            ARCHITECTURE maxpld OF t_ff IS
            BEGIN
                process(clk)
                    begin
                        if (clk='1' and clk'event) then 
                            if (t='1') then
                                q <= not(q);
                            else
                                q <= q;   
                            end if;
                        end if;
                end process;       
            END maxpld;