-- Tri-state Buffer.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;

            ENTITY tristate IS
            port ( a, enable : in std_logic;
                                 q : out std_logic);
            END tristate;

            ARCHITECTURE maxpld OF tristate IS
            BEGIN
                process(a, enable)
                begin
                    if (enable ='1') then 
                        q <= a;
                    else
                        q <= 'Z';   
                    end if;
                end process;       
            END maxpld;
 

   [VHDL 2]

            -- Tri-state Buffer_1.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;
         
            ENTITY tristate_1 IS
                port ( a, enable : in std_logic;
                                     q : out std_logic);
            END tristate_1;

            ARCHITECTURE maxpld OF tristate_1 IS 

            BEGIN
                q <= a when (enable='1') else 'Z';
            END maxpld;