-- Mealy Machine1.vhd

            LIBRARY ieee;
            USE ieee.std_logic_1164.all;

            ENTITY fsm1 IS
            port ( x, clk  : in std_logic;
                        z     : out std_logic);
            END fsm1;

            ARCHITECTURE maxpld OF fsm1 IS
            type state is (s0, s1, s2, s3);
            signal st : state;
            BEGIN
                process(clk)
                begin
                    if (clk='1' and clk'event) then
                        if (x='0') then 
                            z <= '0';
                        else
                            case st is
                                 when s0 => st <= s1;
                                         z <= '0';
                                 when s1 => st <= s2;
                                         z <= '0';
                                 when s2 => st <= s3;
                                         z <= '0';
                                 when s3 => st <= s0;
                                         z <= '1';
                            end case;
                        end if;
                    end if;
                end process;
            END maxpld;